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S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
November. 1999. Ver. 0.1
Prepared by:
Sangho Park
mrno1@samsung.co.kr
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641 Specification Revision History Version 0.0 0.1 Original
The content of page 21 has been modified
Content
Date Aug.1999 Nov.1999
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6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
CONTENTS
INTRODUCTION ................................................................................................................................................. 4 FEATURES ......................................................................................................................................................... 4 BLOCK DIAGRAM .............................................................................................................................................. 5 PIN ASSINGMENTS............................................................................................................................................ 6 PIN DESCRIPTIONS ........................................................................................................................................... 7 OPERATION DESCRIPTION............................................................................................................................... 8 DISPLAY DATA TRANSFER ............................................................................................................................ 8 EXTENSION OF OUTPUT ............................................................................................................................... 8 RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE .................................................. 9 ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 18 RECOMMENDED OPERATION CONDITIONS.................................................................................................. 18 DC CHARACTERISTICS................................................................................................................................... 19 AC CHARACTERISTICS................................................................................................................................... 20 WAVEFORMS ................................................................................................................................................... 21 RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD ........................ 22
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S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
INTRODUCTION
The S6C0641 is a 300 channel or 309 channel output, TFT-LCD source driver for 64 gray scale displays. Data input is based on digital input consisting of 6 bits by 3 dots, which can realize a full-color display of 260,000 colors by output of 64 values gamma-corrected. This device has an internal D/A (Digital-to-Analog) converter for each output and 9 or 11 external power supplies. S6C0641 can be adopted to larger panel, and SHL (Shift Direction Selection) pin makes use of the LCD panel connection conveniently. Maximum operation clock frequency is 55 MHz at a 3.3 V logic operation. It can be applied to the TFT-LCD panel of SVGA, XGA standards.
FEATURES
* * * * * * * * * * * TFT active matrix LCD source driver LSI 64 gray scale is possible through 9 or 11 external power supply and D/A converter Line inversion display is possible CMOS level input Compatible with gamma-correction Logic supply voltage: 3.0 - 5.5 V LCD driver supply voltage: 3.0 - 5.5 V Output dynamic range: 2.6 - 5.1 Vp-p Maximum operating frequency: fMAX = 55 MHz (internal data transmission rate at 3.3 V operation) Output: 300 / 309 outputs TCP available
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6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
BLOCK DIAGRAM
Y309 Y308 Y307 Y003 Y002 6 6 Y001 6 6 DIO1
Output Buffer
VGMA1 VGMA11
11
D/A Converter
6
6
6
6
CLK1
Data Latch
6
6
6
6
Data Register
D00 - D05 D10 - D15 D20 - D25
6 6 6
Data Control
18
100 / 103 bit Shift Register
CLK2
DIO2
SELT
SHL
TESTB
Figure 1. S6C0641 Block Diagram
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S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
PIN ASSIGNMENTS
Y001 Y002 Y003 Y004
VSS2 VDD2 VGMA10 VGMA8 VGMA6 VGMA4 VGMA2 D05 D04 D03 D02 D01 D00 D15 D14 D13 D12 D11 D10 DIO1 VSS1 SELT CLK2 VDD1 DIO2 CLK1 D25 D24 D23 D22 D21 D20 SHL VGMA1 VGMA3 VGMA5 VGMA7 VGMA9 VGMA11 VDD2 VSS2
S6C0641
Y306 Y307 Y308 Y309 6
Figure 2. S6C0641 Pin Assignments
(Top View)
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
PIN DESCRIPTIONS
Symbol VDD1 VDD2 VSS1 VSS2 Y1 - Y309 D0<0:5> - D2<0:5> Pin Name Logic power supply Driver power supply Logic ground Driver ground Driver outputs Display data input 3.0- 5.5 V 3.0 - 5.5 V Ground (0 V) Ground (0 V) The D/A converted 64 gray scale analog voltage is output. The display data is input with a width of 18 bits, gray-scale data (6 bits) by 3 dots (R,G,B) DX0: LSB, DX5: MSB Description
SHL
This pin controls the direction of shift register in cascade connection. The shift direction of the shift registers is as follows. Shift direction control input SHL = H: DIO1 input, Y1 Y309, DIO2 output SHL = L: DIO2 input, Y309 Y1, DIO1 output Start pulse input / output Start pulse input / output Shift clock input SHL = H: Used as the start pulse input pin. SHL = L: Used as the start pulse output pin. SHL = H: Used as the start pulse output pin. SHL = L: Used as the start pulse input pin. Refer to the shift register's shift clock input. the display data is loaded to the data register at the rising edge of CLK2. Latches the contents of the data register at rising edge and transfers them to the D/A converter. Also, after CLK1 input, clears the internal shift register contents. After 1 pulse input on start, operates normally. CLK1 input timing refers to the "Relationships between CLK1 start pulse (DIO1, DIO2) and blanking period" of the switching characteristic waveform. This pin controls 300CH or 309CH output. SELT = H: 309CH output Y151 to Y159 are useless. SELT = L: 300CH output. Y151 to Y159 are useless. This pin is internally pulled-up.(Rpu = 30 k) Input the gamma corrected power supplies from external source. VDD2 VGMA1 > VGMA2 > ......... > VGMA10 > VGMA11 VSS2 Keep gray-scale power supply unchanged during the gray-scale voltage output. TESTB = H: Normal operation mode TESTB = L: Test mode (OP AMP CUT-OFF) This pin is internally pulled-up.(Rpu = 30k)
DIO1 DIO2 CLK2
CLK1
Latch input
SELT
300 / 309CH output control input
VGMA1 - VGMA11
Gamma corrected power supplies
TESTB
Test input
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S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
OPERATION DESCRIPTION
DISPLAY DATA TRANSFER
When DIO1 (or DIO2) pulse is loaded into internal latch on the rising edge of CLK2, DIO1 (or DIO2) pulse enables the operation of data transfer, so display data is valid on the next rising edge of CLK2. Once all the data of 300 / 309 channels are loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is provided, new display data is valid on the next rising edge of CLK2 after the falling edge of DIO1 (or DIO2).
EXTENSION OF OUTPUT
Output pin can be adjusted to an extended screen by cascade connection. (1) SHL = "L" Connect DIO1 pin of previous stage to the DIO2 pin of next stage and all the input pins except DIO1 and DIO2 are connected together in each device. (2) SHL = "H" Connect DIO2 pin of previous stage to the DIO1 pin of next stage and all the input pins except DIO2 and DIO1 are connected together in each device.
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6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE
The LCD drive output voltages are determined by the input data and 11 gamma corrected power supplies (VGMA1 - VGMA11).
SHL = H
OUTPUT DATA Y1 Y2 First D00 - D05 D10 - D15 D20 - D25 ...... Y3 ...... Y307 Y308 Last D00 - D05 D10 - D15 D20 - D25 Y309
SHL = L
OUTPUT DATA Y1 Y2 Last D00 - D05 D10 - D15 D20 - D25 ...... Y3 ...... Y307 Y308 First D00 - D05 D10 - D15 D20 - D25 Y309
Figure 3. Relationship between Shift Direction and Output Data VDD2 VGMA1 VGMA2
VGMA3
VGMA4 VGMA5 VGMA6 VGMA7 VGMA8 VGMA9 VGMA10 VGMA11 VSS2 00H 07H 0FH 17H 1FH 27H 2FH 37H 3FH
Figure 4. Gamma Correction Curve
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S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value: In case of using 11 levels of Gamma-corrected power supplies (VGMA1 to VGMA11) G/S Output voltage Input data DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 VGMA1 00H VH0 0 0 0 0 0 1 VGMA3 + (VGMA2 - VGMA3) x 6/7 01H VH1 0 0 0 0 1 0 VGMA3 + (VGMA2 - VGMA3) x 5/7 02H VH2 0 0 0 0 1 1 03H VH3 VGMA3 + (VGMA2 - VGMA3) x 4/7 04H 0 0 0 1 0 0 VH4 VGMA3 + (VGMA2 - VGMA3) x 3/7 05H VH5 VGMA3 + (VGMA2 - VGMA3) x 2/7 0 0 0 1 0 1 06H VH6 VGMA3 + (VGMA2 - VGMA3) x 1/7 0 0 0 1 1 0 07H VH7 VGMA3 0 0 0 1 1 1 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VH8 VH9 VH10 VH11 VH12 VH13 VH14 VH15 VH16 VH17 VH18 VH19 VH20 VH21 VH22 VH23 VH24 VH25 VH26 VH27 VH28 VH29 VH30 VH31 VGMA4 + (VGMA3 - VGMA4) x 7/8 VGMA4 + (VGMA3 - VGMA4) x 6/8 VGMA4 + (VGMA3 - VGMA4) x 5/8 VGMA4 + (VGMA3 - VGMA4) x 4/8 VGMA4 + (VGMA3 - VGMA4) x 3/8 VGMA4 + (VGMA3 - VGMA4) x 2/8 VGMA4 + (VGMA3 - VGMA4) x 1/8 VGMA4 VGMA5 + (VGMA4 - VGMA5) x 7/8 VGMA5 + (VGMA4 - VGMA5) x 6/8 VGMA5 + (VGMA4 - VGMA5) x 5/8 VGMA5 + (VGMA4 - VGMA5) x 4/8 VGMA5 + (VGMA4 - VGMA5) x 3/8 VGMA5 + (VGMA4 - VGMA5) x 2/8 VGMA5 + (VGMA4 - VGMA5) x 1/8 VGMA5 VGMA6 + (VGMA5 - VGMA6) x 7/8 VGMA6 + (VGMA5 - VGMA6) x 6/8 VGMA6 + (VGMA5 - VGMA6) x 5/8 VGMA6 + (VGMA5 - VGMA6) x 4/8 VGMA6 + (VGMA5 - VGMA6) x 3/8 VGMA6 + (VGMA5 - VGMA6) x 2/8 VGMA6 + (VGMA5 - VGMA6) x 1/8 VGMA6
NOTE: VDD2VGMA1>VGMA2>VGMA3>VGMA4>VGMA5>VGMA6>VGMA7>VGMA8>VGMA9>VGMA10>VGMA11 VSS2
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S6C0641
Table 2. Relationship between Input Data and Output Voltage Value (Continued) Input data G/S Output voltage DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 1 VGMA7 + (VGMA6 - VGMA7) x 7/8 20H VH32 0 0 0 0 1 1 VGMA7 + (VGMA6 - VGMA7) x 7/8 21H VH33 0 0 0 1 0 1 22H VH34 VGMA7 + (VGMA6 - VGMA7) x 7/8 0 0 0 1 1 1 23H VH35 VGMA7 + (VGMA6 - VGMA7) x 7/8 24H VH36 0 0 1 0 0 1 VGMA7 + (VGMA6 - VGMA7) x 7/8 25H VH37 VGMA7 + (VGMA6 - VGMA7) x 7/8 0 0 1 0 1 1 26H VH38 VGMA7 + (VGMA6 - VGMA7) x 7/8 0 0 1 1 0 1 27H VH39 VGMA7 0 0 1 1 1 1 1 0 1 0 0 0 VGMA8 + (VGMA7 - VGMA8) x 7/8 28H VH40 1 0 1 0 0 1 VGMA8 + (VGMA7 - VGMA8) x 6/8 29H VH41 1 0 1 0 1 0 VGMA8 + (VGMA7 - VGMA8) x 5/8 2AH VH42 1 0 1 0 1 1 2BH VH43 VGMA8 + (VGMA7 - VGMA8) x 4/8 2CH VH44 VGMA8 + (VGMA7 - VGMA8) x 3/8 1 0 1 1 0 0 2DH VH45 VGMA8 + (VGMA7 - VGMA8) x 2/8 1 0 1 1 0 1 2EH VH46 VGMA8 + (VGMA7 - VGMA8) x 1/8 1 0 1 1 1 0 2FH VH47 VGMA8 1 0 1 1 1 1 1 1 0 0 0 0 VGMA9 + (VGMA8 - VGMA9) x 7/8 30H VH48 1 1 0 0 0 1 VGMA9 + (VGMA8 - VGMA9) x 6/8 31H VH49 1 1 0 0 1 0 VGMA9 + (VGMA8 - VGMA9) x 5/8 32H VH50 1 1 0 0 1 1 33H VH51 VGMA9 + (VGMA8 - VGMA9) x 4/8 34H VH52 VGMA9 + (VGMA8 - VGMA9) x 3/8 1 1 0 1 0 0 35H VH53 VGMA9 + (VGMA8 - VGMA9) x 2/8 1 1 0 1 0 1 36H VH54 VGMA9 + (VGMA8 - VGMA9) x 1/8 1 1 0 1 1 0 37H VH55 VGMA9 1 1 0 1 1 1 1 1 1 0 0 0 VGMA10 + (VGMA9 - VGMA10) x 6/7 38H VH56 1 1 1 0 0 1 VGMA10 + (VGMA9 - VGMA10) x 5/7 39H VH57 1 1 1 0 1 0 3AH VH58 VGMA10 + (VGMA9 - VGMA10) x 4/7 1 1 1 0 1 1 3BH VH59 VGMA10 + (VGMA9 - VGMA10) x 3/7 3CH VH60 1 1 1 1 0 0 VGMA10 + (VGMA9 - VGMA10) x 2/7 3DH VH61 VGMA10 + (VGMA9 - VGMA10) x 1/7 1 1 1 1 0 1 3EH VH62 VGMA10 1 1 1 1 1 0 3FH VH63 VGMA11 1 1 1 1 1 1 RGMA (Gamma-Corrected Resistance) Ratio. (if the RGMA1 equals 1) RGMA1 RGMA2 RGMA3 RGMA4 RGMA5 RGMA1 = 2.31 k 1.00 2.00 2.77 1.50 0.90 RGMA6 RGMA7 RGMA8 RGMA9 RGMA10 0.84 0.66 0.84 1.42 1.05
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S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
Table 3. Relationship between Input Data and Output Voltage Value: In case of using 10 levels of Gamma-corrected power supplies (VGMA1 = OPEN) G/S Output voltage Input data DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 VGMA2 00H VH0 0 0 0 0 0 1 VGMA3 + (VGMA2 - VGMA3) x 6/7 01H VH1 0 0 0 0 1 0 VGMA3 + (VGMA2 - VGMA3) x 5/7 02H VH2 0 0 0 0 1 1 03H VH3 VGMA3 + (VGMA2 - VGMA3) x 4/7 04H 0 0 0 1 0 0 VH4 VGMA3 + (VGMA2 - VGMA3) x 3/7 05H VH5 VGMA3 + (VGMA2 - VGMA3) x 2/7 0 0 0 1 0 1 06H VH6 VGMA3 + (VGMA2 - VGMA3) x 1/7 0 0 0 1 1 0 07H VH7 VGMA3 0 0 0 1 1 1 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VH8 VH9 VH10 VH11 VH12 VH13 VH14 VH15 VH16 VH17 VH18 VH19 VH20 VH21 VH22 VH23 VH24 VH25 VH26 VH27 VH28 VH29 VH30 VH31 VGMA4 + (VGMA3 - VGMA4) x 7/8 VGMA4 + (VGMA3 - VGMA4) x 6/8 VGMA4 + (VGMA3 - VGMA4) x 5/8 VGMA4 + (VGMA3 - VGMA4) x 4/8 VGMA4 + (VGMA3 - VGMA4) x 3/8 VGMA4 + (VGMA3 - VGMA4) x 2/8 VGMA4 + (VGMA3 - VGMA4) x 1/8 VGMA4 VGMA5 + (VGMA4 - VGMA5) x 7/8 VGMA5 + (VGMA4 - VGMA5) x 6/8 VGMA5 + (VGMA4 - VGMA5) x 5/8 VGMA5 + (VGMA4 - VGMA5) x 4/8 VGMA5 + (VGMA4 - VGMA5) x 3/8 VGMA5 + (VGMA4 - VGMA5) x 2/8 VGMA5 + (VGMA4 - VGMA5) x 1/8 VGMA5 VGMA6 + (VGMA5 - VGMA6) x 7/8 VGMA6 + (VGMA5 - VGMA6) x 6/8 VGMA6 + (VGMA5 - VGMA6) x 5/8 VGMA6 + (VGMA5 - VGMA6) x 4/8 VGMA6 + (VGMA5 - VGMA6) x 3/8 VGMA6 + (VGMA5 - VGMA6) x 2/8 VGMA6 + (VGMA5 - VGMA6) x 1/8 VGMA6
NOTE: VDD2VGMA1>VGMA2>VGMA3>VGMA4>VGMA5>VGMA6>VGMA7>VGMA8>VGMA9>VGMA10>VGMA11 VSS2
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6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
Table 3. Relationship between Input Data and Output Voltage Value (Continued) G/S Output voltage DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 1 VGMA7 + (VGMA6 - VGMA7) x 7/8 20H VH32 0 0 0 0 1 1 VGMA7 + (VGMA6 - VGMA7) x 7/8 21H VH33 0 0 0 1 0 1 22H VH34 VGMA7 + (VGMA6 - VGMA7) x 7/8 0 0 0 1 1 1 23H VH35 VGMA7 + (VGMA6 - VGMA7) x 7/8 24H VH36 0 0 1 0 0 1 VGMA7 + (VGMA6 - VGMA7) x 7/8 25H VH37 VGMA7 + (VGMA6 - VGMA7) x 7/8 0 0 1 0 1 1 26H VH38 VGMA7 + (VGMA6 - VGMA7) x 7/8 0 0 1 1 0 1 27H VH39 VGMA7 0 0 1 1 1 1 1 0 1 0 0 0 VGMA8 + (VGMA7 - VGMA8) x 7/8 28H VH40 1 0 1 0 0 1 VGMA8 + (VGMA7 - VGMA8) x 6/8 29H VH41 1 0 1 0 1 0 VGMA8 + (VGMA7 - VGMA8) x 5/8 2AH VH42 1 0 1 0 1 1 2BH VH43 VGMA8 + (VGMA7 - VGMA8) x 4/8 2CH VH44 VGMA8 + (VGMA7 - VGMA8) x 3/8 1 0 1 1 0 0 2DH VH45 VGMA8 + (VGMA7 - VGMA8) x 2/8 1 0 1 1 0 1 2EH VH46 VGMA8 + (VGMA7 - VGMA8) x 1/8 1 0 1 1 1 0 2FH VH47 VGMA8 1 0 1 1 1 1 1 1 0 0 0 0 VGMA9 + (VGMA8 - VGMA9) x 7/8 30H VH48 1 1 0 0 0 1 VGMA9 + (VGMA8 - VGMA9) x 6/8 31H VH49 1 1 0 0 1 0 VGMA9 + (VGMA8 - VGMA9) x 5/8 32H VH50 1 1 0 0 1 1 33H VH51 VGMA9 + (VGMA8 - VGMA9) x 4/8 34H VH52 VGMA9 + (VGMA8 - VGMA9) x 3/8 1 1 0 1 0 0 35H VH53 VGMA9 + (VGMA8 - VGMA9) x 2/8 1 1 0 1 0 1 36H VH54 VGMA9 + (VGMA8 - VGMA9) x 1/8 1 1 0 1 1 0 37H VH55 VGMA9 1 1 0 1 1 1 1 1 1 0 0 0 VGMA10 + (VGMA9 - VGMA10) x 6/7 38H VH56 1 1 1 0 0 1 VGMA10 + (VGMA9 - VGMA10) x 5/7 39H VH57 1 1 1 0 1 0 3AH VH58 VGMA10 + (VGMA9 - VGMA10) x 4/7 1 1 1 0 1 1 3BH VH59 VGMA10 + (VGMA9 - VGMA10) x 3/7 3CH VH60 1 1 1 1 0 0 VGMA10 + (VGMA9 - VGMA10) x 2/7 3DH VH61 VGMA10 + (VGMA9 - VGMA10) x 1/7 1 1 1 1 0 1 3EH VH62 VGMA10 1 1 1 1 1 0 3FH VH63 VGMA11 1 1 1 1 1 1 RGMA (Gamma-Corrected Resistance) Ratio. (if the RGMA2 equals 1) RGMA1 RGMA2 RGMA3 RGMA4 RGMA5 RGMA1 = 4.62 k 1.00 1.39 0.75 0.45 RGMA6 RGMA7 RGMA8 RGMA9 RGMA10 0.42 0.33 0.42 0.71 0.53 Input data
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6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
Table 4. Relationship between Input Data and Output Voltage Value: In case of using 10 levels of Gamma-corrected power supplies (VGMA2 = OPEN) G/S Output voltage Input data DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 VGMA3 + (VGMA2 - VGMA3) x 7/8 00H VH0 0 0 0 0 0 1 VGMA3 + (VGMA2 - VGMA3) x 6/8 01H VH1 0 0 0 0 1 0 02H VH2 VGMA3 + (VGMA2 - VGMA3) x 5/8 0 0 0 0 1 1 03H VH3 VGMA3 + (VGMA2 - VGMA3) x 4/8 04H 0 0 0 1 0 0 VH4 VGMA3 + (VGMA2 - VGMA3) x 3/8 05H VH5 0 0 0 1 0 1 VGMA3 + (VGMA2 - VGMA3) x 2/8 06H VH6 VGMA3 + (VGMA2 - VGMA3) x 1/8 0 0 0 1 1 0 07H VH7 VGMA3 0 0 0 1 1 1 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VH8 VH9 VH10 VH11 VH12 VH13 VH14 VH15 VH16 VH17 VH18 VH19 VH20 VH21 VH22 VH23 VH24 VH25 VH26 VH27 VH28 VH29 VH30 VH31 VGMA4 + (VGMA3 - VGMA4) x 7/8 VGMA4 + (VGMA3 - VGMA4) x 6/8 VGMA4 + (VGMA3 - VGMA4) x 5/8 VGMA4 + (VGMA3 - VGMA4) x 4/8 VGMA4 + (VGMA3 - VGMA4) x 3/8 VGMA4 + (VGMA3 - VGMA4) x 2/8 VGMA4 + (VGMA3 - VGMA4) x 1/8 VGMA4 VGMA5 + (VGMA4 - VGMA5) x 7/8 VGMA5 + (VGMA4 - VGMA5) x 6/8 VGMA5 + (VGMA4 - VGMA5) x 5/8 VGMA5 + (VGMA4 - VGMA5) x 4/8 VGMA5 + (VGMA4 - VGMA5) x 3/8 VGMA5 + (VGMA4 - VGMA5) x 2/8 VGMA5 + (VGMA4 - VGMA5) x 1/8 VGMA5 VGMA6 + (VGMA5 - VGMA6) x 7/8 VGMA6 + (VGMA5 - VGMA6) x 6/8 VGMA6 + (VGMA5 - VGMA6) x 5/8 VGMA6 + (VGMA5 - VGMA6) x 4/8 VGMA6 + (VGMA5 - VGMA6) x 3/8 VGMA6 + (VGMA5 - VGMA6) x 2/8 VGMA6 + (VGMA5 - VGMA6) x 1/8 VGMA6
NOTE: VDD2VGMA1>VGMA2>VGMA3>VGMA4>VGMA5>VGMA6>VGMA7>VGMA8>VGMA9>VGMA10>VGMA11 VSS2
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6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
Table 4. Relationship between Input Data and Output Voltage Value (Continued) G/S Output voltage DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 1 VGMA7 + (VGMA6 - VGMA7) x 7/8 20H VH32 0 0 0 0 1 1 VGMA7 + (VGMA6 - VGMA7) x 7/8 21H VH33 0 0 0 1 0 1 22H VH34 VGMA7 + (VGMA6 - VGMA7) x 7/8 0 0 0 1 1 1 23H VH35 VGMA7 + (VGMA6 - VGMA7) x 7/8 24H VH36 0 0 1 0 0 1 VGMA7 + (VGMA6 - VGMA7) x 7/8 25H VH37 VGMA7 + (VGMA6 - VGMA7) x 7/8 0 0 1 0 1 1 26H VH38 VGMA7 + (VGMA6 - VGMA7) x 7/8 0 0 1 1 0 1 27H VH39 VGMA7 0 0 1 1 1 1 1 0 1 0 0 0 VGMA8 + (VGMA7 - VGMA8) x 7/8 28H VH40 1 0 1 0 0 1 VGMA8 + (VGMA7 - VGMA8) x 6/8 29H VH41 1 0 1 0 1 0 VGMA8 + (VGMA7 - VGMA8) x 5/8 2AH VH42 1 0 1 0 1 1 2BH VH43 VGMA8 + (VGMA7 - VGMA8) x 4/8 2CH VH44 VGMA8 + (VGMA7 - VGMA8) x 3/8 1 0 1 1 0 0 2DH VH45 VGMA8 + (VGMA7 - VGMA8) x 2/8 1 0 1 1 0 1 2EH VH46 VGMA8 + (VGMA7 - VGMA8) x 1/8 1 0 1 1 1 0 2FH VH47 VGMA8 1 0 1 1 1 1 1 1 0 0 0 0 VGMA9 + (VGMA8 - VGMA9) x 7/8 30H VH48 1 1 0 0 0 1 VGMA9 + (VGMA8 - VGMA9) x 6/8 31H VH49 1 1 0 0 1 0 VGMA9 + (VGMA8 - VGMA9) x 5/8 32H VH50 1 1 0 0 1 1 33H VH51 VGMA9 + (VGMA8 - VGMA9) x 4/8 34H VH52 VGMA9 + (VGMA8 - VGMA9) x 3/8 1 1 0 1 0 0 35H VH53 VGMA9 + (VGMA8 - VGMA9) x 2/8 1 1 0 1 0 1 36H VH54 VGMA9 + (VGMA8 - VGMA9) x 1/8 1 1 0 1 1 0 37H VH55 VGMA9 1 1 0 1 1 1 1 1 1 0 0 0 VGMA10 + (VGMA9 - VGMA10) x 6/7 38H VH56 1 1 1 0 0 1 VGMA10 + (VGMA9 - VGMA10) x 5/7 39H VH57 1 1 1 0 1 0 3AH VH58 VGMA10 + (VGMA9 - VGMA10) x 4/7 1 1 1 0 1 1 3BH VH59 VGMA10 + (VGMA9 - VGMA10) x 3/7 3CH VH60 1 1 1 1 0 0 VGMA10 + (VGMA9 - VGMA10) x 2/7 3DH VH61 VGMA10 + (VGMA9 - VGMA10) x 1/7 1 1 1 1 0 1 3EH VH62 VGMA10 1 1 1 1 1 0 3FH VH63 VGMA11 1 1 1 1 1 1 RGMA (Gamma-Corrected Resistance) Ratio. (if the sum of RGMA1 and RGMA2 equals 1) RGMA1 RGMA2 RGMA3 RGMA4 RGMA5 RGMA1 + RGMA2 = 5.28 k RGMA6 RGMA7 RGMA8 RGMA9 RGMA10 0.37 0.29 0.37 0.62 0.46 Input data
1.00 1.21 0.66 0.39
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S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
Table 5. Relationship between Input Data and Output Voltage Value: In case of using 9 levels of Gamma-corrected power supplies (VGMA2, VGMA10 = OPEN) G/S Output voltage Input data DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 VGMA3 + (VGMA2 - VGMA3) x 7/8 00H VH0 0 0 0 0 0 1 VGMA3 + (VGMA2 - VGMA3) x 6/8 01H VH1 0 0 0 0 1 0 02H VH2 VGMA3 + (VGMA2 - VGMA3) x 5/8 0 0 0 0 1 1 03H VH3 VGMA3 + (VGMA2 - VGMA3) x 4/8 04H 0 0 0 1 0 0 VH4 VGMA3 + (VGMA2 - VGMA3) x 3/8 05H VH5 0 0 0 1 0 1 VGMA3 + (VGMA2 - VGMA3) x 2/8 06H VH6 VGMA3 + (VGMA2 - VGMA3) x 1/8 0 0 0 1 1 0 07H VH7 VGMA3 0 0 0 1 1 1 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VH8 VH9 VH10 VH11 VH12 VH13 VH14 VH15 VH16 VH17 VH18 VH19 VH20 VH21 VH22 VH23 VH24 VH25 VH26 VH27 VH28 VH29 VH30 VH31 VGMA4 + (VGMA3 - VGMA4) x 7/8 VGMA4 + (VGMA3 - VGMA4) x 6/8 VGMA4 + (VGMA3 - VGMA4) x 5/8 VGMA4 + (VGMA3 - VGMA4) x 4/8 VGMA4 + (VGMA3 - VGMA4) x 3/8 VGMA4 + (VGMA3 - VGMA4) x 2/8 VGMA4 + (VGMA3 - VGMA4) x 1/8 VGMA4 VGMA5 + (VGMA4 - VGMA5) x 7/8 VGMA5 + (VGMA4 - VGMA5) x 6/8 VGMA5 + (VGMA4 - VGMA5) x 5/8 VGMA5 + (VGMA4 - VGMA5) x 4/8 VGMA5 + (VGMA4 - VGMA5) x 3/8 VGMA5 + (VGMA4 - VGMA5) x 2/8 VGMA5 + (VGMA4 - VGMA5) x 1/8 VGMA5 VGMA6 + (VGMA5 - VGMA6) x 7/8 VGMA6 + (VGMA5 - VGMA6) x 6/8 VGMA6 + (VGMA5 - VGMA6) x 5/8 VGMA6 + (VGMA5 - VGMA6) x 4/8 VGMA6 + (VGMA5 - VGMA6) x 3/8 VGMA6 + (VGMA5 - VGMA6) x 2/8 VGMA6 + (VGMA5 - VGMA6) x 1/8 VGMA6
NOTE: VDD2VGMA1>VGMA2>VGMA3>VGMA4>VGMA5>VGMA6>VGMA7>VGMA8>VGMA9>VGMA10>VGMA11 VSS2
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6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
Table 5. Relationship between Input Data and Output Voltage Value (Continued) G/S Output voltage DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 1 VGMA7 + (VGMA6 - VGMA7) x 7/8 20H VH32 0 0 0 0 1 1 VGMA7 + (VGMA6 - VGMA7) x 7/8 21H VH33 0 0 0 1 0 1 22H VH34 VGMA7 + (VGMA6 - VGMA7) x 7/8 0 0 0 1 1 1 23H VH35 VGMA7 + (VGMA6 - VGMA7) x 7/8 24H VH36 0 0 1 0 0 1 VGMA7 + (VGMA6 - VGMA7) x 7/8 25H VH37 VGMA7 + (VGMA6 - VGMA7) x 7/8 0 0 1 0 1 1 26H VH38 VGMA7 + (VGMA6 - VGMA7) x 7/8 0 0 1 1 0 1 27H VH39 VGMA7 0 0 1 1 1 1 1 0 1 0 0 0 VGMA8 + (VGMA7 - VGMA8) x 7/8 28H VH40 1 0 1 0 0 1 VGMA8 + (VGMA7 - VGMA8) x 6/8 29H VH41 1 0 1 0 1 0 VGMA8 + (VGMA7 - VGMA8) x 5/8 2AH VH42 1 0 1 0 1 1 2BH VH43 VGMA8 + (VGMA7 - VGMA8) x 4/8 2CH VH44 VGMA8 + (VGMA7 - VGMA8) x 3/8 1 0 1 1 0 0 2DH VH45 VGMA8 + (VGMA7 - VGMA8) x 2/8 1 0 1 1 0 1 2EH VH46 VGMA8 + (VGMA7 - VGMA8) x 1/8 1 0 1 1 1 0 2FH VH47 VGMA8 1 0 1 1 1 1 1 1 0 0 0 0 VGMA9 + (VGMA8 - VGMA9) x 7/8 30H VH48 1 1 0 0 0 1 VGMA9 + (VGMA8 - VGMA9) x 6/8 31H VH49 1 1 0 0 1 0 VGMA9 + (VGMA8 - VGMA9) x 5/8 32H VH50 1 1 0 0 1 1 33H VH51 VGMA9 + (VGMA8 - VGMA9) x 4/8 34H VH52 VGMA9 + (VGMA8 - VGMA9) x 3/8 1 1 0 1 0 0 35H VH53 VGMA9 + (VGMA8 - VGMA9) x 2/8 1 1 0 1 0 1 36H VH54 VGMA9 + (VGMA8 - VGMA9) x 1/8 1 1 0 1 1 0 37H VH55 VGMA9 1 1 0 1 1 1 1 1 1 0 0 0 VGMA11 + (VGMA9 - VGMA11) x 7/8 38H VH56 1 1 1 0 0 1 VGMA11 + (VGMA9 - VGMA11) x 6/8 39H VH57 1 1 1 0 1 0 3AH VH58 VGMA11 + (VGMA9 - VGMA11) x 5/8 1 1 1 0 1 1 3BH VH59 VGMA11 + (VGMA9 - VGMA11) x 4/8 3CH VH60 VGMA11 + (VGMA9 - VGMA11) x 3/8 1 1 1 1 0 0 3DH VH61 VGMA11 + (VGMA9 - VGMA11) x 2/8 1 1 1 1 0 1 3EH VH62 VGMA11 + (VGMA9 - VGMA11) x 1/8 1 1 1 1 1 0 3FH VH63 VGMA11 1 1 1 1 1 1 RGMA (Gamma-Corrected Resistance) Ratio. (if the sum of RGMA1 and RGMA2 equals 1) RGMA1 RGMA2 RGMA3 RGMA4 RGMA5 RGMA1 + RGMA2 = 5.28 k RGMA6 RGMA7 RGMA8 RGMA9 RGMA10 0.37 0.29 0.37 0.71 Input data
1.00 1.21 0.66 0.39
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S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
ABSOLUTE MAXIMUM RATINGS
Table 6. Absolute Maximum Ratings (VSS1 = VSS2 = 0 V) Parameter Logic supply voltage Driver supply voltage Input voltage Output voltage Operation temperature Storage temperature Symbol VDD1 VDD2 VGMA1 - 10 Others DIO1, 2 Y1 - Y309 Topr Tstg CAUTIONS: If LSIs are stressed beyond those listed above "absolute maximum ratings" , they may be permanently destroyed. These are stress ratings only, and functional operation of the device at these or any other condition beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Turn on power order: VDD1 control signal input VDD2 VGMA1 - VGMA11 Turn off power order: VGMA1 - VGMA11 VDD2 control signal input VDD1 Ratings -0.3 to 6.5 -0.3 to 6.5 -0.3 to VDD2 + 0.3 -0.3 to VDD1 + 0.3 -0.3 to VDD1 + 0.3 -0.3 to VDD2 + 0.3 -20 to 75 -55 to 125 C V Unit
RECOMMENDED OPERATION CONDITIONS
Table 7. Recommended Operation Conditions (Ta = -20 to 75 C, VSS1 = VSS2 = 0 V) Parameter Logic supply voltage Driver supply voltage Gamma corrected voltage Maximum clock frequency Output load capacitance Symbol VDD1 VDD2 VGMA1 - VGMA11 fmax CL Min. 3.0 3.0 VSS2 VDD1 = 3.3 V Typ. 3.3 5.0 Max. 5.5 5.5 VDD2 55 150 Unit V V V MHz pF / PIN
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6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
DC CHARACTERISTICS
Table 8. DC Characteristics (Ta = -20 to 75 C, VDD1 = 3.0 to 5.5 V, VDD2 = 3.0 to 5.5 V, VSS1 = VSS2 = 0 V) Parameter High level input voltage Low level input voltage Input leakage current High level output voltage Low level output voltage Resistor Symbol VIH VIL IL VOH VOL R0 - R62 IVOH Driver output current IVOL Output voltage deviation Output voltage range Logic part dynamic current Driver part dynamic current VO Vyo IDD1 VDD2 = 5.0 V, Vx = 3.5 V, Vyo = 4.5 V VDD2 = 5.0 V, Vx = 1.5 V, Vyo = 0.5 V VSS2 + 0.2 V to VDD2 - 1.5 V Input data: 00H to 3FH VDD1 = 3.0 V (2) VDD1 = 3.0 V, VDD2 = 5.0 V, VGMA1 = 4.5 V, VGMA11 = 0.5 V DIO1 (DIO2), VDD1=3.3V IO = -1.0 mA DIO1 (DIO2), VDD1=3.3V IO = +1.0 mA SHL, CLK2, D00 - D25, CLK1, DIO1 (DIO2) Condition Min. 0.7 VDD1 0 -0.5 VDD1 - 0.5 Rn x 0.7 0.5 VSS2 + 0.2 -1.5 0.5 10 3.5 Typ. Max. VDD1 0.3 VDD1 0.5 V 0.5 Rn x 1.3 -0.5 20 VDD2 - 0.2 5.5 mA mA mV V mA Unit V A
IDD2
-
5.5
7.0
NOTES: 1. Vyo is the output voltage of analog output pins Y1 to Y309. Vx is the voltage applied to analog output pins Y1 to Y309. 2. CLK1 period is defined to be 30 s at fCLK2 = 30 MHz, data pattern = 101010 , (checkerboard pattern), Ta = 25 C
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S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
AC CHARACTERISTICS
Table 9. AC Characteristics (Ta = -20 to 75 C, VDD2 = 3.0 to 5.5 V, VDD1 = 3.0 to 5.5 V, VSS1 = VSS2 = 0 V) Parameter Clock pulse width Clock pulse low period Clock pulse high period Data setup time Data hold time Start pulse setup time Start pulse hold time Start pulse delay time CLK1 setup time Driver output delay time1 Driver output delay time2 CLK1 pulse high period Data invalid period Last data timing CLK1-CLK2 time Symbol PWCLK PWCLK(L) PWCLK(H) tSETUP1 tHOLD1 tSETUP2 tHOLD2 tPLH1 tSETUP3 tPHL1 tPHL2 PWCLK1 tINV tLDT tCLK1-CLK2 Condition (1) (1) (1) (1)
Min. 18 4 4 4 0 4 0 1 2
Typ. 1
Max. 14 3 10 -
Unit
ns
VDD1 = 3.3 V CL = 35 pF (2) (3)
CLK2 period s CLK2 period CLK2 period
DIO1 (2) CLK2 CLK1 CLK2
0 6
-
-
ns ns
NOTES: 1. Input condition (VIH = 0.7 VDD1, VIL = 0.3 VDD1) 2. The value is specified when the drive voltage value reaches the target output voltage level of 90% 3. The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy.
20
PWCLK tINV 1st tHOLD1 VIH VIL LAST-1 LAST PWCLK(L) PWCLK(H)
CLK2
WAVEFORMS
DXX
INVALID DATA tSETUP2 tHOLD2
tSETUP1 1st DATA
DIO1 input (DIO2 input)
DIO2 output (DIO1 output)
tSETUP3 PWCLK1 tPHL1 Target output voltage 90% tPLH1
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
CLK1
Y(1:309) tPHL2
Figure 5. Waveforms
tLDT 0.5VDD1 tSETUP1 LAST DATA tHOLD1 tCLK1-CLK2
Target output voltage
CLK2
CLK1
DXX
INVALID DATA
CLK2
CLK1
S6C0641
21
22
1CLK2(Min.) 0.5VDD1 1CLK2 N-1th DATA INVALID DATA blanking time = Min. 3CLK2 Nth DATA 1st DATA 2nd DATA First data in the next line
S6C0641
CLK2
DIO1 input (DIO2 input)
1CLK2(Max.)
CLK1
DXX
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD
Figure 6. Waveforms
Hold HI-Z Analog output
Last data
CLK2
CLK1
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
Y (1:309)

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